Chapter 35: Transistors and Integrated Circuits

Era span: 1947 transistor → 1971 microprocessor · Difficulty: extreme
Requires: Ch 34 circuit concepts, Ch 20 metrology, extreme chemistry discipline ·
Unlocks: Ch 36, all of Part V

The transistor is the most consequential artifact ever manufactured: trillions now ship yearly, each switching billions of times per second. Its story is a materials-purity crusade — the physics was understood decades before ENGINEERING could deliver it.

35.1 Band Theory in One Paragraph

Quantum mechanics sorts solids by electron band gaps: conductors (overlapping bands), insulators (huge gap), semiconductors (small gap, ~1 eV for silicon). Doping silicon (group IV) with phosphorus (group V: extra electron → n-type) or boron (group III: missing electron/"hole" → p-type) creates controllable charge carriers. A p-n junction conducts one way — rectification from crystal structure itself. Germanium came first (easier purity); silicon won on temperature stability and its miracle oxide.

35.2 The Transistor Trio

• Point-contact (Dec 1947, Bardeen & Brattain): two gold contacts nudged onto germanium crystal showed power gain — proof of principle, maddening to manufacture.
• Junction transistor (Shockley's theory, 1948): sandwich structure — thin base between emitter/collector — where injected minority carriers across the base produce gain. Manufacturable, analyzable, the design that scales.
• Why gain works: small base current commands large collector current; as a SWITCH, saturation/cutoff states encode logic (Ch 36).

35.3 Silicon and the Planar Revolution

Germanium's 80 °C ceiling and leaky junctions capped it. Silicon's higher melting point (1,414 °C) demanded better purification — zone refining (molten zone sweeping impurities along an ingot, segregation coefficients doing the work) and Czochralski/FLOAT-ZONE single-crystal growth delivered it. Then:

• Hoerni's planar process (1959): grow a protective SiO₂ layer; open windows through it photolithographically; dope through windows; the oxide passivates junctions forever after. Devices became surface-stable, batch-fabricated, and RELIABLE.
• Photolithography cycle: photoresist coat → mask exposure → develop → etch/diffuse/ion-implant → strip; repeat per layer. Resolution defines the generation; cleanrooms (dust = killer defects) define the factory.
• Kilby's (1958, germanium, hand-wired hybrid) vs Noyce's (1959, silicon, planar-integrated) integrated circuit race ended with Noyce's architecture winning because it matched manufacturing reality.

35.4 Moore's Law as Business Model

Moore's 1965 observation — component counts doubling roughly every two years — became a self-fulfilling ROADMAP: fabs, equipment makers, and designers synchronized investment to it. The engine underneath:

• Learning-curve economics: costs fall ~25–30 % per cumulative-doubling regardless of technology generation.
• Wafer scale-ups (25 mm → 300 mm), feature shrinks (10 µm → nanometers), yield management (defect density statistics).
• Landmark artifacts: Intel 1103 DRAM (1970, core memory obsoleted), 4004 microprocessor (1971, ~2,300 transistors — a CPU on one chip), then the exponential everything.

35.5 What Semiconductors Demand From Your Civilization

Honest prerequisites list — this chapter fails without them:

1. Chemical purity culture: parts-per-billion contamination control; ultrapure water, process gases, acids (Ch 21).
2. Metrology at microns: microscopy, interferometry, step-height measurement (Ch 20).
3. Vacuum and thin films: sputtering/evaporation deposition, oxidation furnaces with tight temperature control.
4. Photomask fabrication: precision optics + pattern generation (Ch 19 skills industrialized).
5. Statistical process control: yields are probability distributions managed by data (Ch 47). Build X̄–R charts on lot yields and defect tallies exactly as §47.13 specifies — the chart is what turns the 90 %+ stable-yield threshold below from luck into policy, and it feeds straight off the firing-log discipline of Ch 14 and charge logs of Ch 22.

Jump: skip germanium consumer products entirely; go zone-refined silicon straight into planar ICs IF §35.5 exists. Tubes remain necessary ONLY as circuit-concept scaffolding (Ch 34) — their schematics port directly.

Dead end avoided: chasing ever-smaller FEATURES before yield discipline exists. History's losers built beautiful prototypes they couldn't manufacture profitably; the industry belongs to boring reproducibility.

Key threshold: first home-fabbed working logic gate marks entry; stable 90 %+ yields on simple circuits mark industrial arrival. From there, compute compounds exactly as fast as you can shrink and stack — which is the throttle setting for every remaining chapter.

35.6 The Transistor Papers

• Point-contact detectors predate understanding: cat's-whisker crystal sets (silicon/galena, 1900s radio) used semiconductor rectification nobody could explain; WWII radar detector programs (Purdue and elsewhere) industrialized germanium/silicon diode purity — Bell Labs' postwar solid-state group inherited trained physicists AND refined crystals from that war program (Ch 51's spillover ledger).
• December 23, 1947: Bardeen and Brattain's demonstration logged in lab notebooks; the group announcement came June 30, 1948; the Nobel (shared with Shockley) arrived 1956. Shockley's junction-transistor theory (1948) made devices manufacturable — theory completing experiment, textbook sequence.
• Sony before Sony: Tokyo Tsushin Kogyo licensed Western Electric's transistor (1952–53) despite Bell executives' doubts, shipped the TR-55 pocket radio (1955) — Japan's consumer-electronics ascent began with licensed technology plus manufacturing discipline, not indigenous invention.
• The Traitorous Eight (September 1957): eight Shockley Semiconductor Lab researchers resigned over Shockley's management (his Nobel came anyway, 1956); Fairchild Semiconductor resulted; planar process (Hoerni's January 1959 memo), Noyce's IC architecture, Intel (1968, Noyce/Moore/Grove), and venture-capital culture all descend from that resignation letter. Management quality as existential variable, documented in personnel files.
• Kilby v. Noyce: Kilby's September 1958 TI prototype used germanium and hand-added wire; Noyce's January 1959 silicon planar concept matched manufacturing reality; the interference litigation settled with cross-licensing and both men sharing honors. Simultaneous invention resolved by who could FABRICATE — recurring verdict.
• Czochralski discovered his crystal-pulling method accidentally in 1916 when he dipped his pen into molten tin instead of the inkwell; zone refining came from Pfann's Bell Labs work (1952). The wafer supply chain has accident and wartime pedigree stamped through it.

35.7 First Build: The First Home-Fabbed Device

One buildable reference design: a single planar junction device — a silicon p–n diode first, then an aluminum-gate MOSFET on the same process — on a 25 mm wafer. This is deliberately below the §35.5 logic-gate threshold: one junction working proves every discipline; a gate proves four of them at once.

Phase 0 — Silicon supply (zone refining, worked numbers).

1. Start from metallurgical-grade silicon (~98 %); crush, acid-leach in Ch 21 aqua-class acids to strip iron/aluminum.
2. Zone-refine in a floating-zone rig (containerless — no crucible contamination): induction or focused-resistance heated molten zone ≈ ingot diameter, 6–8 passes sweeping ~2 mm/min under argon. - Segregation does the work: impurities with distribution coefficient k ≪ 1 (Fe, Cu, most metals) ride the zone to the tail; cut and discard both ends each run. - Failure mode — boron persists: k(B) = 0.8, zoning barely moves it. Recovery: chemical removal upstream (distilled chlorosilane route) is mandatory for low-resistivity control; zoning alone cannot fix bad feedstock. - Failure mode — polycrystal freeze: sweep too fast cracks the zone → drop to 1.5 mm/min, stabilize zone power before advancing.
3. Pull or float-zone a single crystal; target 10 Ω·cm n-type wafers, lapped, then chem-mech polished to mirror.

Verification checkpoint: four-point probe resistivity within spec across the wafer AND etched cross-section shows single-crystal lattice under microscope (Ch 19) — resistivity without crystallinity fails silently later.

Phase 1 — Cleanroom discipline.

4. First fab runs at ISO Class 7 overall (~Class 10,000: HEPA ceiling, ≥60 air changes/hour) with an ISO Class 5 laminar-flow bench (0.45 m/s face velocity) for all open-wafer handling.
5. Rule that governs everything: any particle ≥ ~1/10 of minimum feature size is a killer defect — for µm features, police ≥0.5 µm particles religiously; full suits, no paper, no wood.

Verification checkpoint: witness wafers left open on the bench 30 min show zero added particles of killing size under dark-field inspection.

Wafer clean (run before every furnace step). The documented RCA sequence, adjusted only in container material (polymer tubs — never soda glass, that is sodium again):

1. Organic/particle strip: NH₄OH : H₂O₂ : H₂O at 1 : 1 : 5, 75 °C, 10 min.
2. DI rinse.
3. Metal-ion strip: HCl : H₂O₂ : H₂O at 1 : 1 : 6, 75 °C, 10 min.
4. Final DI rinse; dry under filtered nitrogen. Tongs only; both baths are aggressively oxidizing — vent them.

Skip this and every later failure mode below gets more likely at once.

Phase 2 — First photolithography cycle (worked parameters).

6. Grow mask oxide: wet steam oxidation, 1,000 °C, ~60 min → ≈0.5 µm SiO₂; measure by interference color chart.
7. Spin coat: positive photoresist, 4,000 rpm / 30 s → ~1 µm film (edge bead wiped after).
8. Soft bake: 95 °C hotplate, 60 s.
9. Expose: contact print against chrome-on-glass mask under Hg g-line (436 nm); dose 100–200 mJ/cm² — with a measured 10 mW/cm² lamp, 10–20 s. Calibrate dose on a step-wedge coupon once; never guess twice.
10. Develop: 2.38 % TMAH (metal-ion-free), 60 s with gentle agitation; DI rinse.
11. Hard bake: 110–120 °C, 2 min.
12. Etch oxide through windows: buffered HF (6:1 NH₄F:HF), ~100 nm/min at room temperature — time from measured thickness +25 % overetch, then calibrate the bath weekly on a witness coupon rather than trusting any printed rate.
13. Resist strip in acetone/oxidizer chemistry; inspect.

Per-step failure modes:

• Resist lifts during develop: soft bake skipped/short → re-deposit; bake discipline is not optional.
• Undercut grass (oxide fuzz in windows): over-etched past clearing → shorten next batch; verify endpoint on a half-etched witness.
• Random window failures: particle at exposure → trace via the Phase 1 witness wafers; fix airflow before blaming chemistry.
• Pinholes in mask oxide: dirty pre-oxidation surface → add the Phase 1 wafer clean before furnace; repeat offender = contaminated glassware, not chemistry.

Mask quality gates everything. The first mask can be drawn at 10:1 scale and photoreduced through Ch 19 optics onto high-contrast plate — but inspect it under magnification before every exposure run: a mask defect replicates onto EVERY die on EVERY wafer, converting one flaw into a systematic yield loss that charts will (correctly) flag as an assignable cause. Keep two masks per layer: working and master; retire scratched working copies. Log bath temperatures beside etch timestamps — rate drift hides there first.

Verification checkpoint: oxide thickness ±10 % of target across wafer, window edges vertical under high-power inspection, no lifting resist — this cycle repeated three times identically IS §35.5's "boring reproducibility."

Phase 3 — Junction and transistor completion.

14. Diode route: dope through windows (diffusion or deposited-dopant anneal to target sheet resistance), evaporate aluminum through a third mask, alloy contacts at ~450 °C for 15 min.
15. MOSFET route adds a gate step before metal: grow dry gate oxide, 1,000 °C, ~45 min → ≈80 nm (dry oxidation grows slower and cleaner than the wet mask oxide of Phase 2 — never reuse a wet-grown layer under a gate), open source/drain windows by repeating Phase 2's lithography, dope to heavy concentration, then metallize gate/source/drain in one aluminum evaporation from a tungsten filament.
16. Test without exotic gear: an oscilloscope plus isolating transformer and series resistors plots I–V families (a curve tracer in disguise). Diode acceptance: forward knee ~0.6 V, reverse leakage below µA range at rated voltage. MOSFET acceptance: drain current switching cleanly with gate voltage; threshold read where drain current crosses a fixed µA-class reference at fixed V_DS.

Per-step failure modes:

• Gate shorts: pinholes in thin gate oxide → stricter pre-gate clean, slower furnace ramps; discard affected die rather than rework.
• Threshold drifts between measurements: mobile sodium ions wandering in the oxide (sweat, soda glassware) → this is why development specified metal-ion-free TMAH, not NaOH (Phase 2, step 10); enforce gloves and polymer labware.
• Ohmic contact refuses: under-doped contact regions spike or rectify → raise surface doping at contacts, re-alloy.

Verification checkpoint: diode curves repeatable across five sibling die within ±10 %; MOSFET threshold stable over an hour of bias — stability, not peak performance, is the acceptance bar per §35.5.

Final acceptance — Key threshold: one junction is entry-level proof; repeat §35.5's real bar by building the same stack into a resistor-loaded logic gate with stable 90 %+ lot yield, charts running per §47.13.