Chapter 35: Transistors and Integrated Circuits

Era span: 1947 transistor → 1971 microprocessor · Difficulty: extreme
Requires: Ch 20, Ch 21, Ch 34
Unlocks: Ch 36, Ch 38, Ch 40, Ch 41, Ch 42, Ch 43, Ch 44, Ch 45, Ch 46

The transistor is the most-manufactured artifact in history and among the most consequential: single chips now carry billions, each switching billions of times per second. Its story is a materials-purity crusade — the physics was understood decades before ENGINEERING could deliver it.

35.1 Band Theory in One Paragraph

Quantum mechanics sorts solids by electron band gaps: conductors (overlapping bands), insulators (huge gap), semiconductors (small gap, ~1 eV for silicon). Doping silicon (group IV) with phosphorus (group V: extra electron → n-type) or boron (group III: missing electron/"hole" → p-type) creates controllable charge carriers. A p-n junction conducts one way — rectification from crystal structure itself. Germanium came first (easier purity); silicon won on temperature stability and its miracle oxide.

35.2 The Transistor Family

• Point-contact (Dec 1947, Bardeen & Brattain): two gold contacts nudged onto germanium crystal showed power gain — proof of principle, maddening to manufacture.
• Junction transistor (Shockley's theory, 1948): sandwich structure — thin base between emitter/collector — where injected minority carriers across the base produce gain. Manufacturable, analyzable, the design that scales.
• Why gain works: small base current commands large collector current; as a SWITCH, saturation/cutoff states encode logic (Ch 36).
• The MOSFET (Atalla and Kahng, Bell Labs, 1959–60) — the transistor that won: a metal gate over a thin layer of silicon oxide controls the channel beneath it by its electric field alone, drawing almost no gate current. It depended on Atalla's grown-oxide passivation of silicon (§35.3) and is simpler to build in planar layers than the junction sandwich. Wanlass's complementary MOS (CMOS, 1963) pairs n-channel and p-channel devices so that a logic gate draws significant power only while it switches. MOSFETs in CMOS logic and memory are the billions-per-chip transistors behind this chapter's opening claim.

35.3 Silicon and the Planar Revolution

Germanium's 80 °C ceiling and leaky junctions capped it. Silicon's higher melting point (1,414 °C) demanded better purification — zone refining (molten zone sweeping impurities along an ingot, segregation coefficients doing the work) and Czochralski/FLOAT-ZONE single-crystal growth delivered it. The feedstock itself starts as quartz: reduced with carbon in an electric-arc furnace to metallurgical-grade silicon of roughly 98–99 % purity, converted to a volatile chloride (trichlorosilane), distilled, and deposited as ultrapure polysilicon on heated rods (the Siemens process, late 1950s) — the "nine nines" material that crystal pulling needs (§35.7 treats it as a qualified material, not a percentage). Then:

• Hoerni's planar process (1959): grow a protective SiO₂ layer; open windows through it photolithographically; dope through windows; the oxide passivates junctions forever after. Devices became surface-stable, batch-fabricated, and RELIABLE.
• Photolithography cycle: photoresist coat → mask exposure → develop → etch/diffuse/ion-implant → strip; repeat per layer. Resolution defines the generation; cleanrooms (dust = killer defects) define the factory.
• Kilby's (1958, germanium, hand-wired hybrid) vs Noyce's (1959, silicon, planar-integrated) integrated circuit race ended with Noyce's architecture winning because it matched manufacturing reality.

35.4 Moore's Law as Business Model

Moore's 1965 observation — component counts doubling roughly every year, revised in 1975 to every two years — became a self-fulfilling ROADMAP: fabs, equipment makers, and designers synchronized investment to it. The engine underneath:

• Learning-curve economics: costs fall ~25–30 % per cumulative-doubling regardless of technology generation.
• Wafer scale-ups (25 mm → 300 mm), feature shrinks (10 µm → nanometers), yield management (defect density statistics).
• Landmark artifacts: Intel 1103 DRAM (1970, core memory obsoleted), 4004 microprocessor (1971, ~2,300 transistors — a CPU on one chip), then the exponential everything.

35.5 What Semiconductors Demand From Your Civilization

Honest prerequisites list — this chapter fails without them:

1. Chemical purity culture: parts-per-billion contamination control; ultrapure water, process gases, acids (Ch 21).
2. Metrology at microns: microscopy, interferometry, step-height measurement (Ch 20).
3. Vacuum and thin films: sputtering/evaporation deposition, oxidation furnaces with tight temperature control.
4. Photomask fabrication: precision optics + pattern generation (Ch 19 skills industrialized).
5. Statistical process control: yields are probability distributions managed by data (Ch 47). Chart per §47.13 by data type: X̄–R for dimensions and film thicknesses measured at several sites per wafer, an I-MR or p-chart for one yield figure per lot, and c-charts for defect counts — the chart is what turns the 90 %+ stable-yield threshold below from luck into policy, and it feeds straight off the firing-log discipline of Ch 14 and charge logs of Ch 22.

Jump: skip germanium consumer products entirely; go zone-refined silicon straight into planar ICs IF §35.5 exists. Tubes remain necessary ONLY as circuit-concept scaffolding (Ch 34) — their schematics port directly.

Dead end avoided: chasing ever-smaller FEATURES before yield discipline exists. History's losers built beautiful prototypes they couldn't manufacture profitably; the industry belongs to boring reproducibility.

Key threshold: a first working logic gate from a qualified facility (§35.7) marks entry; stable 90 %+ yields on simple circuits mark industrial arrival. From there, compute compounds exactly as fast as you can shrink and stack — which is the throttle setting for every remaining chapter.

35.6 The Transistor Papers

• Point-contact detectors predate understanding: cat's-whisker crystal sets (silicon/galena, 1900s radio) used semiconductor rectification nobody could explain; WWII radar detector programs (Purdue and elsewhere) industrialized germanium/silicon diode purity — Bell Labs' postwar solid-state group inherited trained physicists AND refined crystals from that war program (Ch 51's spillover ledger).
• December 23, 1947: Bardeen and Brattain's demonstration logged in lab notebooks; the group announcement came June 30, 1948; the Nobel (shared with Shockley) arrived 1956. Shockley's junction-transistor theory (1948) made devices manufacturable — theory completing experiment, textbook sequence.
• Sony before Sony: Tokyo Tsushin Kogyo licensed Western Electric's transistor (1952–53) despite Bell executives' doubts, shipped the TR-55 pocket radio (1955) — Japan's consumer-electronics ascent began with licensed technology plus manufacturing discipline, not indigenous invention.
• The Traitorous Eight (September 1957): eight Shockley Semiconductor Lab researchers resigned over Shockley's management (months after his 1956 Nobel); Fairchild Semiconductor resulted; planar process (Hoerni's January 1959 memo), Noyce's IC architecture, Intel (1968, Noyce/Moore/Grove), and venture-capital culture all descend from that resignation letter. Management quality as existential variable, documented in personnel files.
• Kilby v. Noyce: Kilby's September 1958 TI prototype used germanium and hand-added wire; Noyce's January 1959 silicon planar concept matched manufacturing reality; the interference litigation settled with cross-licensing and both men sharing honors. Simultaneous invention resolved by who could FABRICATE — recurring verdict.
• Czochralski discovered his crystal-pulling method accidentally in 1916 when he dipped his pen into molten tin instead of the inkwell; zone refining came from Pfann's Bell Labs work (1952). The wafer supply chain has accident and wartime pedigree stamped through it.

35.7 Qualification Gate: From Controlled Semiconductors to a Fabrication Line

Semiconductor fabrication is not a home-fab craft simply because a single junction can be made on a small wafer. A credible facility must control feedstock purity, water, particles, surface preparation, photoresist chemistry, masks, etch rates, dopant profile, oxidation, metal interfaces, contamination, waste, and electrical acceptance across repeated lots. HF, TMAH, peroxide baths, solvents, high-temperature furnaces, toxic and pyrophoric process gases, vacuum systems, and electrical supplies create professional hazards.

Competence gate: semiconductor chemistry, vacuum, high-voltage, gas systems, occupational hygiene, and process control require trained specialists and an approved facility procedure. The general manual explains the system and acceptance discipline; it does not provide a complete fabrication recipe or certify a home laboratory.

Facility and feedstock gates

1. Silicon supply is a qualified material, not a percentage. Record supplier, grade, oxygen/carbon/metallic impurities, resistivity, crystallinity, orientation, surface condition, and lot history. Zone refining improves some impurities but does not remove every contaminant or defect; industrial feedstock routes may be required.
2. Cleanroom classification is a performance requirement, not a label. Commission HEPA systems, airflow, pressure relationships, room recovery, particle monitoring, gowning, material transfer, and maintenance under an approved contamination-control plan. “Zero particles” is not a credible acceptance claim; define detection limits and statistical criteria.
3. Chemical recipes are process-control documents. Record purity, lot, concentration, temperature, time, agitation, container material, waste treatment, and emergency response. Semiconductor cleaning chemistry can change with substrate and equipment; historical RCA recipes are starting points, not universal SOPs.
4. Photolithography is calibrated end to end. Coat thickness, adhesion, exposure dose, focus, development, etch rate, selectivity, undercut, mask dimensions, and inspection all require witness coupons and measurement. A dose guessed from a lamp wattage is not a process setpoint.
5. Doping and oxidation are profile processes. Sheet resistance alone does not prove junction depth, activation, oxide thickness, interface quality, or reliability. Use qualified electrical and physical measurements.
6. Metallisation requires pattern transfer and interface tests. Contact resistance, leakage, adhesion, alloying, corrosion, and thermal cycling matter as much as continuity.
7. Device acceptance precedes line acceptance. Characterise diode or transistor curves over temperature and bias, compare sibling devices statistically, and investigate outliers. A fabrication line becomes credible after repeated lots meet defect, yield, reliability, and traceability criteria.

Minimum process record

Each lot records material identity, recipe revision, operator, equipment, tool status, calibration, environment, measured process variables, deviations, test data, yield, defects, and disposition. A failed lot is quarantined and investigated; results are never edited to make acceptance look cleaner.

Final acceptance: a line is ready for higher-complexity devices only when repeated process-control records, calibrated instruments, independent process checks, statistical yield, defect learning, maintenance, waste control, and emergency systems agree. First-device success is a milestone, not evidence that industrial fabrication has been reproduced.